Teaching

Hardware Foundations of AI: From Physical Devices to Computing Architecture

The course starts from the physics of semiconductor devices and builds up to chip architecture: how transistors and memory devices work, the behaviour of emerging devices such as memristors and phase-change memory, how those devices form computing units, and how computing units are organised into architectures that can run neural networks. One question runs throughout: where does the compute for AI actually come from, and what limits it?

The course ranked 3rd among more than forty Yuanpei electives in teaching evaluation, and its materials were selected for Peking University's digital textbook programme.

Topics

• Semiconductor device fundamentals and the physical limits of scaling
• Memory hierarchy and the origins of the memory bottleneck
• Physical behaviour of emerging non-volatile devices and its computational meaning
• Principles and trade-offs of compute-in-memory
• Dataflow and parallelism in neural network accelerators
• Efficiency evaluation: from device metrics to system metrics

Intelligent Hardware Architecture

Taking an architectural view, the course asks what intelligent workloads demand of hardware and where existing architectures fall short. It covers processor fundamentals, memory systems, networks-on-chip and domain-specific accelerator design, using the lab's own work to discuss design trade-offs in emerging architectures.

Topics

• Instruction sets and microarchitecture; pipelining and parallelism
• Caches and memory systems; quantitative analysis of the memory wall
• Network-on-chip topology, routing and flow control
• Neural network accelerators: systolic arrays, dataflow and scheduling
• Designing domain-specific architectures: from workload analysis to parameters
• Case studies: differentiable neural computers, neural ODEs, coding chips

AI-Based Digital System Design

This course responds to a pressing challenge: as Moore's law reaches its limits and chip complexity grows exponentially, traditional hand-written HDL design struggles to close an optimal PPA loop, with long development cycles and slow iteration. The course focuses on AI-based digital front-end design and aims to break down disciplinary barriers, training people who understand both logic design and timing analysis and who think in terms of "AI for Hardware".

Students learn to use machine learning models to generate design code for digital integrated circuits and systems from the simple to the complex, driving automated translation from natural-language requirements to hardware logic, and to carry out parameter optimisation, congestion prediction, dataflow evaluation and power optimisation in order to improve hardware performance and shorten iteration cycles. Working on real problems, they address PPA optimisation in actual circuit and architecture design, develop an engineering outlook grounded in industry–academia collaboration, and become digital front-end designers fluent in AI-enabled toolchains.

Format and assessment

Lectures, with three labs, a midterm project and a final project:

• Lab 1: combinational logic
• Lab 2: sequential logic and state machines
• Lab 3: AI-assisted verification
• Midterm project: systolic array in an AI chip and its state machine design
• Final project: complex system-level NoC integration