研究团队
People
Students are recruited and supervised jointly with the School of Integrated Circuits, the Institute for Artificial Intelligence and partner groups, and work across devices, circuits, architecture and algorithms.
Principal investigator
Yaoyu Tao 陶耀宇
School of Integrated Circuits and Institute for Artificial Intelligence, Peking University
Assistant Professor · Researcher · Doctoral Supervisor
Boya Young Fellow · National high-level young talent · Huawei Weiming Young Scholar · BAAI Qingyuan Scholar
He received his bachelor's degree from Shanghai Jiao Tong University, his master's from Stanford University and his PhD from the University of Michigan, all in electrical and computer engineering. He previously worked as a CPU circuit design engineer at Oracle and as a staff research scientist at Qualcomm, and joined Peking University in 2022. His work centres on intelligent chip architecture and integrated circuit design for AI, communication coding and brain–computer interfaces.
Contact taoyaoyutyy@pku.edu.cn ｜ Micro-Nano Electronics Bldg. 323, Ziyuan West Bldg. 2208B
Research
The work follows two threads. The first is high-performance operator circuits on beyond-Moore devices: for bottleneck operators in AI computation — Fourier transforms, frequency conversion, sorting, distance metrics — the group proposes reconfigurable multi-physics device circuits, including the first comparator-free sort-in-memory circuit, the first volatile/non-volatile hetero-integrated Fourier transform circuit, the first in-situ frequency conversion circuit, a millisecond-scale phase-change memristor neural dynamical chip and a mixed-precision CIM chip for embodied AI. These appear as first or corresponding author in Science, Nature Electronics, Nature Communications, MICRO, IEDM and National Science Review.
The second is distributed heterogeneous networks-on-chip that break the concurrency bottleneck of AI chips across diverse workloads. On the communication side this produced the first parallel split-tree polar coding architecture chip (3.25 Gbps, a record at the time) and a nonbinary LDPC parity-check architecture that addressed the long-standing error-floor problem. On the AI side it produced HiMA (39.1× faster than the fastest AI chip of its time), a neural-ODE architecture with early exit (2.6× speedup), and a CIM instruction set with an end-to-end validation framework that has been deployed in Huawei's computing product line with up to 16.6× speedup.
Impact
- More than 50 papers, 14 as first author and 17 as corresponding author; over 20 Chinese and US patents filed or granted.
- Related patented technology is used in chips at Texas Instruments, Qualcomm and Huawei, with over 100 million units shipped; the beyond-Moore operator circuit IP ships to Huawei and the AI computing circuit IP is in trial use at Alibaba DAMO Academy.
- The work has been cited as representative by Muriel Médard, Erdal Arıkan, Naresh Shanbhag, Xiaohu You, Andreas Burg and Warren Gross, and by Huawei, Qualcomm and SK hynix in their commercial patents.
- Nominated for the 2025 Top-10 Semiconductor Research Advances and the 2025 Top-10 Chip Science Advances in China; covered by People's Daily, Xinhua, Guangming Daily, Yahoo and Science News (English summary).
- Leads NSFC Excellent Young Scientists (Overseas), General Program and Major Research Plan projects, two National Key R&D projects, a Beijing NSF non-consensus project, and industrial projects with Huawei and Vertilite.
Service and teaching
- Editorial board member, Nature npj Unconventional Computing (2024–); IEEE Transactions on Circuits and Systems I (2019); IEEE Young Professionals in CAS (2019).
- Technical program committee member for MICRO, HPCA and ISCAS; reviewer for Nature, Nature Electronics, Nature Communications, IEEE JSSC, IEDM, VLSI, FPGA, MICRO, HPCA and TCAS-I.
- Teaches "Intelligent Hardware Architecture" and "Hardware Foundations of AI" at Yuanpei College and "AI-Based Digital System Design" at the School of EECS; ranked 3rd among forty-plus Yuanpei electives and selected for PKU's digital textbook programme.
Education and appointments
| Period | Institution | Role |
|---|---|---|
| 2022.07 – present | Peking University, School of Integrated Circuits and Institute for AI | Researcher, doctoral supervisor, Boya Young Fellow |
| 2017.02 – 2022.06 | Qualcomm, Wireless Chip R&D | Staff research scientist (part-time while studying, 2017.02–2019.06) |
| 2015.10 – 2016.09 | Oracle | CPU circuit design engineer |
| PhD, 2022 | University of Michigan, Electrical and Computer Engineering | Advisor: Zhengya Zhang |
| MS, 2015 | Stanford University, Electrical Engineering | Advisor: Amin Arbabian |
| BS, 2013 | Shanghai Jiao Tong University, Electrical and Computer Engineering | Advisor: Shensheng Zhang |
Awards
- 2025 Top-10 Chip Science Advances in China (nominee); 2025 Top-10 Semiconductor Advances in China (nominee)
- 2025 Huawei Weiming Young Scholar Award; 2024 Huawei Computing Product Line Best Technical Collaboration Award
- 2024 Best Presentation Award, 26th CIE Youth Conference
- 2023 National high-level young talent; 2023 Wiley Open Science Excellent Author Award
- 2022 Peking University Boya Young Fellow; 2022 BAAI Qingyuan Scholar
- 2021 IEEE Globecom Best Paper Award; Qualcomm Technology Star Award in 2019, 2020 and 2021
- 2019 IEEE VLSI Best Paper Award nomination; 2013 IEEE ISCAS Best Paper Award nomination
- 2018 Rackham Science Research STG Award, University of Michigan; 2015 First Prize, Stanford Analog Devices analog circuit design competition
Members
Members below are jointly supervised with partner groups. Years in parentheses indicate the period of involvement; alumni are shown in a lighter style.
Postdoctoral researchers
PhD students
Master's students
Undergraduate researchers
Who we are looking for
Integrated circuits
Familiar with digital or analogue design flows, with experience in RTL, layout or silicon bring-up — and interested in why a circuit is slow and where the power goes.
Architecture and systems
A background in compilers, simulators or high-performance computing, and a willingness to rethink what the instruction and memory model should look like for a new kind of hardware.
Algorithms and devices
Experience in machine learning, signal processing or device physics, and an interest in matching algorithmic structure to device behaviour.
An imperfect match is still worth a conversation. Most projects here span two or three layers, and what matters most is a willingness to spend time in the layer you do not yet know. See Contact for how to apply.