技术资料
Resources
Toolchains, circuit IP and patents accumulated through our research, together with reference material for new members.
Design and validation toolchain
Cross-layer research only works if each layer can be checked against the others. The lab maintains a continuous chain from device models to end-to-end applications, so that a change at any layer can be quantified at all the rest.
Tools and frameworks
- Compact device model library Memristor, phase-change memory and VO2 models fitted to measured data, including conductance drift, write variation and cycling degradation, ready to plug into circuit simulation.
- Compute-in-memory architecture simulator Multi-core simulation of digital compute-in-memory, reporting accuracy, power and latency at both operator and application level.
- End-to-end validation framework Compatible with Huawei Kunpeng and Ascend simulators, so architectural designs can be evaluated directly on industry software stacks.
- CIM instruction set and compiler support Four vector instruction classes form a complete operator set exposing a CUDA-like interface; the accompanying mapping tool partitions the compute graph between digital and CIM cores.
- Automated FPGA prototyping framework Rapid prototyping for complex coding algorithms such as nonbinary LDPC, with parameterised generation and automated regression testing.
- Optoelectronic mapping tool A neural network hardware mapping method for VCSEL optical accelerators that decides at compile time which computations run in the optical domain.
Circuit IP and translation
- Beyond-Moore operator circuit IP Shipped to Huawei and others; received the 2024 Huawei Computing Product Line Best Technical Collaboration Award, given to only five projects a year.
- AI computing circuit IP In trial deployment at Alibaba DAMO Academy.
- Coding and decoding circuit IP Related patents are used in chips at Texas Instruments, Qualcomm and Huawei, with more than 100 million units shipped.
- End-to-end compute-in-memory solution Deployed in Huawei's computing product line with up to 16.6× speedup.
Patents
Over 20 Chinese and US patents filed or granted, covering compute-in-memory circuits, optoelectronic fusion architecture, device programming and reliability, algorithm quantization and neuromorphic devices.
Titles below are English renderings; the Chinese patents are registered under their original Chinese titles. Numbers are as filed.
| Title | Region | Patent / application no. | Inventors |
|---|---|---|---|
| LDPC post-processor architecture and method for low error floor conditions | US | US9793923B2 | Yaoyu Tao; Joyce Kwong |
| LDPC post-processor architecture and method for low error floor conditions | CN | ZL201680064534.8 | Yaoyu Tao; Joyce Kwong |
| Fully analogue dataflow neural ODE solver and its computing method | CN | CN202411573862.3（CN119577297B） | Yuchao Yang, Yuli Sun, Yaoyu Tao, Lianfeng Yu |
| Finite-field error-correction coding method and system for compute-in-memory systems | CN | CN202311037278.1 | Yaoyu Tao, Daijing Shi, Yuchao Yang, Bonan Yan |
| Optoelectronic fusion heterogeneous computing architecture and method for LLM acceleration | CN | CN2026111081170 | Zelun Pan, Yaoyu Tao, Yiming Wang, Meng Li, Teng Zhang |
| Transimpedance-amplifier-free cascaded compute-in-memory circuit based on RRAM and VCSEL | CN | CN202611089775X | Yiming Wang, Yaoyu Tao, Zelun Pan, Teng Zhang, Meng Li |
| Neural network hardware mapping method for VCSEL optical computing accelerators | CN | CN2026111626613 | Yiming Wang, Yaoyu Tao, Zelun Pan, Meng Li, Teng Zhang |
| Nested dynamic mixed-precision quantization for mixture-of-experts models | CN | CN2026108744760 | Meng Li, Renjie Wei, Haochen Huang, Jinqi Wen, Yaoyu Tao, Teng Zhang |
| Data processing system | CN | CN202310639274.4 | Yuchao Yang, Xiaoming Zhu, Yaoyu Tao, Yihang Zhu et al. |
| Operator compilation method and apparatus | CN | CN202311070464.5 | Yuchao Yang, Xiaoming Zhu, Yaoyu Tao, Yihang Zhu et al. |
| Trigonometric function implementation based on memristors | CN | CN202411249930.0 | Yuchao Yang, Yihang Zhu, Yaoyu Tao |
| Cloth simulation acceleration system and method on a memristor CIM architecture | CN | CN2024115995707 | Yuchao Yang, Jie Long, Yaoyu Tao, Lianfeng Yu |
| CNN weight mapping and pixel-level inference simulation on a memristor CIM architecture | CN | CN2024112760540 | Yuchao Yang, Zhiyuan Li, Yaoyu Tao, Yihang Zhu, Lei Cai |
| Memristor-based large-model CIM acceleration and its dataflow processing method | CN | CN202410781014.5 | Yuchao Yang, Yihang Zhu, Yaoyu Tao, Zhaokun Jing |
| Finite-state-machine write verification scheme for memristive devices | CN | CN2024108261130 | Yuchao Yang, Lianfeng Yu, Yaoyu Tao, Yuxiang Yang |
| Programmable multi-timescale reservoir computing unit and its operation method | CN | CN2024107436937 | Yuchao Yang, Zhen Yang, Teng Zhang, Yaoyu Tao, Ru Huang |
| Fully parallel vector outer-product computation on electrochemical RAM | CN | CN2024107436922 | Yuchao Yang, Zhen Yang, Yingming Lu, Yaoyu Tao, Teng Zhang, Ru Huang |
| Tunable LIF neuron hardware unit based on electrochemical doping | CN | CN2024108200368 | Yuchao Yang, Zhen Yang, Teng Zhang, Yaoyu Tao, Ru Huang |
| DRAM refresh method based on memristors | CN | CN2025113632008 | Yuchao Yang, Bonan Yan, Yaoyu Tao, Anjunyi Fan et al. |
| Wear levelling across multiple RRAM cores for endurance | CN | CN2025113620246 | Yuchao Yang, Bowen Wang, Quan Zhang, Longhao Yan, Daijing Shi, Zelun Pan, Yaoyu Tao et al. |
| Digital compute-in-memory circuit and method based on memristors | CN | CN2025112241952 | Yuchao Yang, Longhao Yan, Zelun Pan, Yaoyu Tao |
| In-place binary conversion unit integrating non-volatile multi-level memory with transistors | CN | CN2025106180167 | Yuchao Yang, Zhen Yang, Teng Zhang, Yaoyu Tao |
Getting started
New members usually need to fill gaps in two or three layers. These are our usual starting points; specific reading lists and slides are shared within the group.
Architecture
Standard texts on processor microarchitecture and memory systems, plus a reading list of recent MICRO, HPCA and ISCA papers on compute-in-memory and accelerators.
Integrated circuits
Digital and analogue IC design fundamentals, with emphasis on memory array peripherals, low-power ADCs and mixed-signal verification.
Devices and algorithms
Reviews of memristor and phase-change memory physics, and the original papers behind the algorithms the lab uses most, from neural ODEs to coding theory.
Each term the lab runs a short lecture series for new members that ties these three threads together; the notes stay in the group document library.