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• 2026.09

  Programmable spatial optoelectronic heterogeneous AI inference chip presented at the Pujiang Innovation Forum

  The 19th Pujiang Innovation Forum's Special Forum on Silicon Photonics Innovation and Development was held at the Zhangjiang Science Hall in Shanghai. The PKU Xingyao Yuedong team, winner of first prize in the team category of the second Zhangjiang Cup Silicon Photonics Innovation and Entrepreneurship Competition, received its award at the forum, where Yaoyu Tao presented the team's programmable spatial optoelectronic heterogeneous AI inference chip. The design combines digital optical-intensity accumulation, a short optical path that separates multiplication and accumulation, three-dimensional electrical–optical–electrical heterogeneous integration, and an in-house flow-control compiler for low-error, low-loss and programmable AI inference. The team has completed multiple tape-out validation rounds and built a compilation and deployment framework, with a focus on low-latency edge inference. STAR Market DailyIT Times (reprint)China Securities JournalYouth DailyShanghai Securities News (via Tencent News)Shanghai municipal service platform

• 2026.09

  Two compute-in-memory chip papers at ESSERC 2026

  Two works were presented in the compute-in-memory session of the IEEE European Solid-State Electronics Research Conference in Mallorca, Spain: a hybrid analog-digital RRAM CIM system built on 4T2R1C charge-domain analog CIM cells with reinforcement-learning-driven mixed-precision deployment, and a 40nm phase-change CIM chip supporting POSIT/INT mixed precision for edge foveated rendering at 3.58 mJ per frame. Program

• 2026.08

  PhD student Zelun Pan wins first prize at the 9th China Postgraduate IC Innovation Competition

  At the national finals of the Huawei Cup competition in Shenzhen, Zelun Pan won a first prize, ranking among the top 18 teams nationwide. Homepage

• 2026.07

  PiMM-NoC memristor in-memory network-on-chip at DAC 2026

  PiMM-NoC is a process-in-memristor-memory network-on-chip for versatile AI models, paired with a reinforcement-learning mapping framework; it was presented on 29 July in the in-memory and near-memory computing session. Yaoyu Tao is a co-first and co-corresponding author. Program

• 2026.07

  Neural dynamical system chip published in Science

  Together with Prof. Yuchao Yang's group at Peking University and Prof. Zhitang Song's group at SIMIT, CAS, the team built the world's first millisecond-scale neural dynamical system chip based on phase-change memristors. By exploiting conductance drift and multi-level conductance, the adaptive integration step search is mapped directly onto the physical evolution of the devices; in a 40nm process, single-step latency falls to 2.12 ms, 3.82–36.27× faster and 11.75–24.73× lower power than dedicated accelerators, with end-to-end cortical reconstruction 50.38–478.18× faster than an A100 GPU. Science ran an accompanying perspective describing this as a shift toward physics-driven computing. Lei Cai, Yaoyu Tao, Chenchen Xie and Longhao Yan are co-first authors; Yaoyu Tao is a co-corresponding author. DOIEurekAlert!TechXploreCGTN

• 2026.02

  Homogeneous integration of optoelectronic neurons and ferroelectric synapses in Nature Communications

  For neuromorphic vision, two-dimensional-material optoelectronic neurons and ferroelectric synapses are integrated homogeneously on one process platform, so that optical sensing and early processing happen at the sensor and less data has to move. Yaoyu Tao is a co-corresponding author. DOIPKU ECE newsSearch

• 2026.02

  High-concurrency tri-mode memristor ODE solver in Nature Communications

  Three solving modes — coarse, fine and a coarse-to-fine look-ahead — allow arbitrary ordinary differential equation systems to be solved without reprogramming. Built on a taped-out memristor chip with a PCB and FPGA demonstration platform, the system reaches 601–6920× speedup and 1710–3930× better energy efficiency than CPU/GPU on exponential functions, the Lorenz equations and the three-body problem. PhD student Lianfeng Yu is first author; Yaoyu Tao and Yuchao Yang are corresponding authors. DOI

• 2026.01

  First hetero-integrated memristor Fourier transform system in Nature Electronics

  HIFT combines volatile and non-volatile memristors into a high-throughput spectral computing architecture. A VO₂ volatile array generates arbitrary-radix spectral waveforms in situ at up to 1.74 MHz with 50 Hz resolution, while a TaO_x/HfO_x multi-level array performs signed in-memory multiply–accumulate. The system supports uniform and non-uniform 1D/2D discrete Fourier transforms up to radix 2048 at 99.2% accuracy and 504.3 GS/s, up to 96.98× beyond existing hardware. Lei Cai, Yaoyu Tao, Teng Zhang and Chang Liu are co-first authors; Yaoyu Tao is a co-corresponding author. DOI

• 2025.12

  Three papers at IEDM 2025

  A 40nm mixed-precision phase-change memory chip with digital compute-in-memory and adaptive drift compensation for embodied AI, cutting programming latency by 63.3% and computation loss by 13.1×; an 8Mb learning-aware RRAM CIM accelerator for embodied self-supervised learning; and efficient multimodal fusion on a 64-core phase-change CIM processor with predictive programming. Mixed-precision PCM8Mb RRAM

• 2025.11

  NSFC General Program grant approved; A-SSCC 2025 paper published

  The NSFC General Program project on high-concurrency neural-ODE compute-in-memory chips runs from January 2026 to December 2029. In the same month, a 28nm mixed-precision edge accelerator developed with Prof. Meng Li's group appeared at IEEE A-SSCC 2025, reaching 534.6 TOPS/W using stochastic computing for embodied AI. Search

• 2025.10

  Huawei Weiming Young Scholar Award

  In the same year the lab received Huawei Young Talent Program funding for next-generation chip architecture research, and began a collaboration with Huawei's data communication product line on low-power FEC.

• 2025.09

  VO₂ Turing-instability coupling system at ESSERC 2025; local active memristive oscillator in National Science Review

  The first work harnesses Turing instability in a VO₂-based negative-feedback coupling system to produce controllable complex dynamics; the second demonstrates controllable complex behaviour and frequency-domain feature extraction in a locally active memristive oscillator. Both provide the device basis for later frequency-domain operator circuits. NSR paper

• 2025.07

  Reconfigurable sort-in-memory system in Nature Electronics

  The first compute-in-memory hardware system for high-complexity sorting. Using the bit-read mechanism of a 1T1R memristor array, the team proposed comparator-free tree-node-skipping (TNS) and cross-array TNS schemes supporting a range of data sizes and types. Measurements show 7.70× higher throughput, 160.4× better energy efficiency and 32.46× better area efficiency than conventional sorting systems, demonstrated on Dijkstra shortest-path search and in-situ pruned neural network inference. PhD student Lianfeng Yu is first author; Yaoyu Tao and Yuchao Yang are co-corresponding authors. The result was nominated for the 2025 Top-10 Semiconductor Research Advances in China. DOITechXplorearXiv

• 2025.05

  Invited lecture; 128Mb PCM in-memory object detection in Advanced Science

  Invited talk in the Lushan Lecture series at Hunan University of Technology and Business. In the same period, work with SIMIT on in-memory object detection using a 128Mb carbon-doped Ge₂Sb₂Te₅ phase-change memory chip appeared in Advanced Science, and an efficient pipeline programming scheme for CNNs on a 40nm PCM CIM chip was presented at IEEE EDTM 2025. Search

• 2025.03

  PROCA probabilistic processing architecture at HPCA 2025; Beijing NSF project approved

  Developed with Prof. Bonan Yan's group, PROCA is a programmable probabilistic processing unit for causal inference that accelerates sampling through accept/reject prediction and multicore pipelining, reaching 42–1058× speedup over GPUs. The same month, the Beijing Natural Science Foundation non-consensus project on higher-order dynamical chip architecture beyond the Turing machine was approved. Search

• 2025.01

  Physical unclonable in-memory computing in Nature Communications

  The first on-chip integrated physically unclonable compute-in-memory scheme, with a new coding approach for edge in-memory neural network acceleration that protects input, weights and network structure at low hardware cost. Yaoyu Tao is a co-author. Search

• 2024.12

  Huawei Best Technical Collaboration Award; dual-mode PCM CIM chip at IEDM 2024

  The beyond-Moore operator circuit IP shipped to Huawei and other companies, earning the 2024 Huawei Computing Product Line Best Technical Collaboration Award, given to only five projects a year. In the same month, neural manifold learning on a 40nm dual-mode (current- and charge-domain) phase-change CIM chip with hardware adaptive drift compensation was presented at IEDM 2024, achieving a 476× energy efficiency gain. Search

• 2024.11

  MeMCISA in-memory database instruction set at MICRO 2024

  Selection, join and aggregation are pushed into the memristor array and organised around memory, forming an instruction set abstraction for database workloads. PhD student Yihang Zhu is first author; Yaoyu Tao and Yuchao Yang are co-corresponding authors. Search

• 2024.08

  Scalable universal Ising machine in Nature Electronics

  Built on an in-house 40nm embedded memristor process, this in-memory Ising computing chip solves arbitrary Ising-graph combinatorial optimisation problems with interaction-centric storage and computation, giving 4.56–7.32× speedup on max-cut and 442–1450× on graph colouring versus GPUs. Yaoyu Tao is a co-author. DOI

• 2024.06

  Dendritic neurons with high-density RRAM in Advanced Functional Materials; van der Waals optical hetero-synapses in Advanced Materials

  The first integrates trainable dendritic neurons with a high-density RRAM chip for fully hardware memristive neuromorphic computing; the second proposes configurable optical hetero-synapses based on full van der Waals bipolar ferroelectric structures for in-sensor computing, with Yaoyu Tao as a co-corresponding author. Search

• 2024.02

  VO₂ memristor in-situ frequency converter in Nature Communications

  An 8×8 array of consistent, calibratable VO₂ memristive oscillators performs frequency synthesis and mixing in situ with compact peripheral circuits, handling 2–8 channels of low-frequency IoT signals up to 48 kHz and cutting end-to-end wireless IoT energy by 1.45–1.94×. Yaoyu Tao is a co-corresponding author. DOI

• 2024.01

  Two major research plan sub-projects launched

  An NSFC Major Research Plan key sub-project on heterogeneous compute-in-memory architecture fusing SRAM and RRAM, and a National Key R&D "Matter Manipulation" project on prototype photonic devices, both began.

• 2023.09

  Selected for the national high-level young talent programme

  Also received the Wiley Open Science Excellent Author award; the NSFC Excellent Young Scientists Fund (Overseas) project on hardware–software co-designed chip architecture with advanced devices was ongoing.

• 2023.06

  Arvon heterogeneous system-in-package at VLSI 2023 and in JSSC

  Developed with Prof. Zhengya Zhang's group at the University of Michigan and Intel, Arvon integrates a 14nm FPGA with two 22nm 1.8 TFLOPS/W DSP chiplets over a 1.7 Tbps/mm² AIB 2.0 interface for versatile workload acceleration. Yaoyu Tao is a co-author. Search

• 2023.02

  eNODE at HPCA 2023; neural-ODE FPGA acceleration at FPGA 2023

  eNODE targets edge inference and training of neural ordinary differential equations with an early-exit mechanism, 2.6× faster than the fastest AI chip at the time (co-first author). The FPGA work introduces two-stage structured pruning with history-based stepsize search, giving over 2.6× speedup on Virtex-7 (corresponding author). The same year saw integrated memristor networks for physiological signal processing (Advanced Electronic Materials) and dynamic memristive reservoir computing for seizure detection (APL Machine Learning). eNODEFPGA paper

• 2022.07

  Joined Peking University and founded LEAP-PKU

  Joined the Institute for Artificial Intelligence and the School of Integrated Circuits, and was named a Boya Young Fellow of Peking University and a Qingyuan Scholar of the Beijing Academy of Artificial Intelligence in the same year.

• 2022.05

  Two papers at ISCAS 2022

  A high-throughput split-tree architecture for nonbinary SCL polar decoding (first author), and fast, scalable memristive in-memory sorting with a column-skipping algorithm (corresponding author) — the starting point for the later sort-in-memory system. Split-tree arXivColumn-skipping arXiv

• 2021.12

  HiMA at MICRO 2021; Globecom 2021 Best Paper Award

  HiMA gives differentiable neural computers a distributed, history-based memory access engine; with the distributed DNC-D model almost all memory operations stay local, and post-synthesis in 40nm it is 6.47× and 39.1× faster than the fastest memory-augmented neural network accelerators of the time, and up to 2646× faster than an RTX 3080Ti. The DNC-aided SCL-flip polar decoding work won the IEEE Globecom Best Paper Award among more than three hundred papers. The same year brought a third Qualcomm Technology Star award. HiMA arXivDNC-aided arXiv

• 2021.02

  Configurable split-tree polar decoder in JSSC

  The VLSI 2019 architecture was extended into a full journal paper giving the architecture and 40nm silicon measurements for configurable successive-cancellation list decoding. It has since been cited by Erdal Arıkan, Muriel Médard and Naresh Shanbhag as representative work in this area. Search

• 2019.06

  3.25 Gbps configurable split-tree polar decoder chip at VLSI 2019

  In 40nm CMOS with an area of 0.64 mm² and 13.2 pJ/b efficiency, the chip reached 3.25 Gbps, the highest throughput reported at the time, and was nominated for the best paper award. The same year, efficient LDPC post-processors appeared in TCAS-I and an automated FPGA prototyping framework for nonbinary LDPC codes at ISCAS 2019. TCAS-I arXivFPGA framework arXiv

• 2012–2015

  Nonbinary LDPC decoder chip series

  From a high-throughput nonbinary LDPC decoding architecture at ISCAS 2012 (first author), through a 1.15 Gb/s fully parallel decoder at ISSCC 2013 and a 4.68 Gb/s belief-propagation polar decoder at VLSI 2014, to a fully parallel decoder with fine-grained dynamic clock gating in JSSC 2015 — a body of chip work addressing the LDPC error-floor problem. The ISCAS 2013 in-situ error detection paper was nominated for a best paper award. JSSC 2015