Peking University School of Integrated Circuits Institute for Artificial Intelligence Join us 中文
LEAP PKU

Lab for Emerging Architecture and Processor

Peking University 北京大学-后摩尔芯片架构与集成电路实验室

学术发表

Publications

Papers are grouped into first/corresponding-author work and collaborative work, ordered roughly by significance and date within each group. Lab members are shown in bold.

Venues of first and corresponding-author papers
Authorship roles across papers

More than 50 papers in total, 14 as first author and 17 as corresponding author. Each entry below carries a publisher DOI, an arXiv preprint or a Google Scholar search link.

First and corresponding-author papers

Includes first-author, co-first-author, corresponding and co-corresponding author papers. Co-first marks a co-first author and Corresp. a corresponding or co-corresponding author.

01 Lei Cai, Yaoyu Tao, Chenchen Xie, Longhao Yan, Shiqian Li, Ruihong Shen, Zelun Pan, Xile Wang, Bowen Wang, Daijing Shi, Yihang Zhu, Teng Zhang, Yixin Zhu, Xi Li, Zhitang Song, Ru Huang, Yuchao Yang. A sub-10-millisecond neural dynamical system based on phase-change memristors. Science, 2026, 393(6806): 105–112. Co-firstCorresp. DOI Search
02 Lei Cai, Yaoyu Tao, Teng Zhang, Chang Liu, Pek Jun Tiw, Lianfeng Yu, Zelun Pan, Longhao Yan, Haoyang Luo, Yihang Zhu, Bowen Wang, Bonan Yan, Xiyuan Tang, Ru Huang, Yuchao Yang. A first-principle hetero-integrated Fourier transform system based on memristors. Nature Electronics, 2025. Co-firstCorresp. DOI Search
03 Lianfeng Yu, Teng Zhang, Zeyu Wang, Xile Wang, Zelun Pan, Bowen Wang, Zhaokun Jing, Jiaxin Liu, Yuqi Li, Ziang Xie, Yihang Zhu, Bonan Yan, Yaoyu Tao, Yuchao Yang. Fast and reconfigurable sort-in-memory system enabled by memristors. Nature Electronics, 2025, 14: 1076. Corresp. DOI arXiv Search
04 Jiarong Wang, Keqin Liu, Pek Jun Tiw, Dawei He, Lianfeng Yu, Bowen Wang, Jinxuan Bai, Teng Zhang, Xin Shan, Yang Yang, Yuzhe Wang, Yongsheng Wang, Yaoyu Tao, Xiaoxian Zhang, Yuchao Yang. Homogeneous integration of two-dimensional material-based optoelectronic neurons and ferroelectric synapses for neuromorphic vision. Nature Communications, 2026, 17(1): 1373. Corresp. DOI Search
05 Chang Liu, Pek Jun Tiw, Teng Zhang, Yanghao Wang, Lei Cai, Rui Yuan, Zelun Pan, Wenshuo Yue, Yaoyu Tao, Yuchao Yang. VO2 memristor-based frequency converter with in-situ synthesize and mix for wireless internet-of-things. Nature Communications, 2024, 15: 1523. Corresp. DOI Search
06 Lianfeng Yu, Teng Zhang, Yang Han, Bowen Wang, Ziang Xie, Haochen Zhang, Jiaxin Liu, Longhao Yan, Pek Jun Tiw, Daijing Shi, Lei Cai, Yaoyu Tao, Yuchao Yang. High-concurrency tri-mode memristor-based ODE solver. Nature Communications, 2025. Corresp. DOI Search
07 Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang. A configurable successive-cancellation list polar decoder using split-tree architecture. IEEE Journal of Solid-State Circuits (JSSC), 2020, 56(2): 612–623. First author Search
08 Yaoyu Tao, Zhengya Zhang. HiMA: A fast and scalable history-based memory access engine for differentiable neural computer. IEEE/ACM International Symposium on Microarchitecture (MICRO), 2021: 845–856. First author arXiv Search
09 Yihang Zhu, Lei Cai, Lianfeng Yu, Anjunyi Fan, Longhao Yan, Zhaokun Jing, Bonan Yan, Yaoyu Tao, Yuchao Yang. MeMCISA: Memristor-enabled memory-centric instruction-set architecture for database systems. IEEE/ACM International Symposium on Microarchitecture (MICRO), 2024: 1678–1692. Corresp. Search
10 Junkang Zhu, Yaoyu Tao, Zhengya Zhang. eNODE: Energy-efficient and low-latency edge inference and training of neural ODEs. IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2023: 802–813. Co-first Search
11 Ziang Xie, Yaoyu Tao, Zelun Pan, Haojun Chen, Zhiyuan Li, Qinghao Wang, Zhiming Pan, Yihang Zhu, Zixiang Luo, Yian Yang, Mo Guang, Kaiwen Long, Yaodong Yang, Yuchao Yang. PiMM-NoC: Process-in-memristor-memory NoC with RL mapping framework for versatile AI models. ACM/IEEE Design Automation Conference (DAC), 2026. Co-firstCorresp. Program Search
12 Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang. A 3.25 Gb/s, 13.2 pJ/b, 0.64 mm2 configurable successive-cancellation list polar decoder using split-tree architecture in 40nm CMOS. IEEE Symposium on VLSI Circuits, 2019: C240–C241. First authorBest paper nomination Search
13 Zelun Pan, Longhao Yan, Xile Wang, Bowen Wang, Yueying Luo, Zhe Zhan, Xi Li, Yuqi Li, Lei Cai, Teng Zhang, Minghui Yin, Yaoyu Tao, Zhitang Song, Yuchao Yang. A 40nm mixed-precision PCM chip with fused analog/digital compute-in-memory and adaptive drift compensation for embodied AI applications. IEEE International Electron Devices Meeting (IEDM), 2025. Corresp. Search
14 Yaoyu Tao, Zhengya Zhang. DNC-aided SCL-flip decoding of polar codes. IEEE Global Communications Conference (Globecom), 2021: 1–6. First authorBest paper award arXiv Search
15 Yaoyu Tao, Shuanghong Sun, Zhengya Zhang. Efficient post-processors for improving error-correcting performance of LDPC codes. IEEE Transactions on Circuits and Systems I (TCAS-I), 2019, 66(10): 4032–4043. First author arXiv Search
16 Jinxuan Bai, Dawei He, Bingjie Dang, Keqin Liu, Zhen Yang, Jiarong Wang, Xiaoxian Zhang, Yongsheng Wang, Yaoyu Tao, Yuchao Yang. Full van der Waals bipolar ferroelectric configurable optical hetero-synapses for in-sensor computing. Advanced Materials, 2024, 36(50): 2401060. Corresp. Search
17 Lei Cai, Jing Wang, Lianfeng Yu, Bonan Yan, Yaoyu Tao, Yuchao Yang. Accelerating neural-ODE inference on FPGAs with two-stage structured pruning and history-based stepsize search. ACM International Symposium on Field-Programmable Gate Arrays (FPGA), 2023: 177–183. Corresp. Search
18 Yang Han, Lianfeng Yu, Yaoyu Tao, Yuchao Yang. MGPA: A memristor-based genome processing accelerator for single-cell RNA sequencing. Design, Automation and Test in Europe Conference (DATE). Corresp. Search
19 Lianfeng Yu, Zhaokun Jing, Yuchao Yang, Yaoyu Tao. Fast and scalable memristive in-memory sorting with column-skipping algorithm. IEEE International Symposium on Circuits and Systems (ISCAS), 2022: 590–594. Corresp. arXiv Search
20 Lei Cai, Lianfeng Yu, Wenshuo Yue, Yihang Zhu, Zhiyu Yang, Yuqi Li, Yaoyu Tao, Yuchao Yang. Integrated memristor network for physiological signal processing. Advanced Electronic Materials, 2023, 9(6): 2300021. Corresp. Search
21 Zhiyu Yang, Keqin Liu, Rui Yuan, Xulei Wu, Lei Cai, Teng Zhang, Yaoyu Tao, Yufeng Jin, Yuchao Yang. Seizure detection using dynamic memristor-based reservoir computing and leaky integrate-and-fire neuron for post-processing. APL Machine Learning, 2023, 1: 046123. Corresp. Search
22 Yaoyu Tao, Cedric Choi. High-throughput split-tree architecture for nonbinary SCL polar decoder. IEEE International Symposium on Circuits and Systems (ISCAS), 2022: 2057–2061. First author arXiv Search
23 Yaoyu Tao, Qi Wu. An automated FPGA-based framework for rapid prototyping of nonbinary LDPC codes. IEEE International Symposium on Circuits and Systems (ISCAS), 2019. First author arXiv Search
24 Yaoyu Tao, Youn Sung Park, Zhengya Zhang. High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders. IEEE International Symposium on Circuits and Systems (ISCAS), 2012: 2625–2628. First author Search

Collaborative papers

Work carried out jointly with groups in devices, materials and systems.

01 Wenshuo Yue, Teng Zhang, Zhaokun Jing, Kai Wu, Yuxiang Yang, Zhen Yang, Yongqin Wu, Weihai Bu, Kai Zheng, Jin Kang, Yibo Lin, Yaoyu Tao, Bonan Yan, Ru Huang, Yuchao Yang. Scalable universal Ising machine enabled by interaction-centric storage and compute-in-memory technology. Nature Electronics, 2024. DOI Search
02 Wenshuo Yue, Kai Wu, Zhiyuan Li, Juchen Zhou, Zeyu Wang, Teng Zhang, Yuxiang Yang, Lintao Ye, Yongqin Wu, Weihai Bu, Shaozhi Wang, Xiaodong He, Xiaobing Yan, Yaoyu Tao, Bonan Yan, Ru Huang, Yuchao Yang. Physical unclonable in-memory computing for simultaneously protecting private data and deep learning models. Nature Communications, 2025. Search
03 Daijing Shi, Yihan Fu, Yihang Zhu, Anjunyi Fan, Yaoyu Tao, Bonan Yan, Yuchao Yang. Correcting processing-in-memory multiply-accumulate arithmetic errors with LDPC. npj Unconventional Computing, 2026. DOI arXiv Search
04 Daijing Shi, Hongxiao Zhao, Yihan Fu, Zhan Chen, Jiayi Li, Yihang Zhu, Anjunyi Fan, Yaoyu Tao, Yuchao Yang, Bonan Yan. MCHA: A memory-centric hierarchical architecture for parallel-sequential computing. IEEE/ACM International Symposium on Microarchitecture (MICRO), 2026. To appear Program Search
05 Youn Sung Park, Yaoyu Tao, Zhengya Zhang. A fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. IEEE Journal of Solid-State Circuits (JSSC), 2014, 50(2): 464–475. Search
06 Youn Sung Park, Yaoyu Tao, Zhengya Zhang. A 1.15 Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. IEEE International Solid-State Circuits Conference (ISSCC), 2013: 422–423. Search
07 Youn Sung Park, Yaoyu Tao, Shuanghong Sun, Zhengya Zhang. A 4.68 Gb/s belief propagation polar decoder with bit-splitting register file. IEEE Symposium on VLSI Circuits, 2014: 1–2. Search
08 Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, et al. Arvon: A heterogeneous system-in-package integrating FPGA and DSP chiplets for versatile workload acceleration. IEEE Journal of Solid-State Circuits (JSSC), 2023. Search
09 Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, et al. Arvon: A heterogeneous SiP integrating a 14nm FPGA and two 22nm 1.8 TFLOPS/W DSPs with 1.7 Tbps/mm2 AIB 2.0 interface. IEEE Symposium on VLSI Circuits, 2023: C7-1. Search
10 Yihan Fu, Anjunyi Fan, Wenshuo Yue, Hongxiao Zhao, Daijing Shi, Qiuping Wu, Jiayi Li, Xiangyu Zhang, Yaoyu Tao, Yuchao Yang, Bonan Yan. PROCA: Programmable probabilistic processing unit architecture with accept/reject prediction and multicore pipelining for causal inference. IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2025. Search
11 Longhao Yan, Zhe Zhan, Zelun Pan, Bowen Wang, Yaoyu Tao, Yuchao Yang. An 8Mb learning-aware RRAM compute-in-memory accelerator for embodied self-supervised learning. IEEE International Electron Devices Meeting (IEDM), 2025. Search
12 Longhao Yan, Zitong Zheng, Xi Li, Xile Wang, Zhe Zhan, Jiukai Fang, Minghui Yin, Zelun Pan, Song Jia, Yaoyu Tao, Zhitang Song, Yuchao Yang. Efficient multimodal fusion with intelligent predictive programming based on 64-core PCM compute-in-memory processor. IEEE International Electron Devices Meeting (IEDM), 2025. Search
13 Longhao Yan, Yuqi Li, Xi Li, Zelun Pan, Zeyu Wang, Xile Wang, Bowen Wang, Zhe Zhan, Xiyuan Tang, Yaoyu Tao, Woo-Ping Ge, Zhitang Song, Yuchao Yang, Ru Huang. Neural manifold learning based on 40nm dual-mode PCM compute-in-memory chip with hardware adaptive drift compensation. IEEE International Electron Devices Meeting (IEDM), 2024. Search
14 Zhen Yang, Wenshuo Yue, Chang Liu, Yaoyu Tao, Pek Jun Tiw, Longhao Yan, Yuxiang Yang, Teng Zhang, Bingjie Dang, Keqin Liu, Xiaodong He, Yongqin Wu, Weihai Bu, Kai Zheng, Jin Kang, Ru Huang, Yuchao Yang. Fully hardware memristive neuromorphic computing enabled by the integration of trainable dendritic neurons and high-density RRAM chip. Advanced Functional Materials, 2024: 2405618. Search
15 Longhao Yan, Qingyu Wu, Xi Li, Chenchen Xie, Xilin Zhou, Yuqi Li, Daijing Shi, Lianfeng Yu, Teng Zhang, Yaoyu Tao, Bonan Yan, Min Zhong, Zhitang Song, Yuchao Yang, Ru Huang. Neural architecture search with in-memory multiply–accumulate and in-memory rank based on coating layer optimized C-doped Ge2Sb2Te5 phase change memory. Advanced Functional Materials, 2023: 2300458. Search
16 Chenchen Xie, Yuqi Li, Longhao Yan, Sannian Song, Houpeng Chen, Ruijuan Qi, Xi Li, Yihang Zhu, Lianfeng Yu, Bonan Yan, Yaoyu Tao, Gaoming Feng, Yuchao Yang, Zhitang Song. Memristive in-memory object detection with 128Mb C-doped Ge2Sb2Te5 PCM chip. Advanced Science, 2025: e05678. Search
17 Yanghao Wang, Pek Jun Tiw, Yuheng Liu, Yaoyu Tao, Teng Zhang, Yuchao Yang. Local active memristive oscillator enables controllable complex behaviors and frequency domain extraction. National Science Review (NSR), 2025. Search
18 Yingming Lu, Zhen Yang, Yaoyu Tao, Lei Cai, Teng Zhang, Longhao Yan, Ru Huang, Yuchao Yang. Energy-efficient online training with in situ parallel computing on electrochemical memory arrays. Advanced Intelligent Systems, 2025: 2401068. Search
19 Bowen Wang, Longhao Yan, Xiyuan Tang, Xile Wang, Yuqi Li, Zeyu Wang, Zelun Pan, Daijing Shi, Zhe Zhan, Yaoyu Tao, Zhitang Song, Yuchao Yang. A scalable charge-domain CIM macro with 2T1R1C cells and capacitor reuse method. IEEE Integrated Circuits and Systems (ICS), 2026. Early Access IEEE Xplore Search
20 Tengyu Zhang, Tong Xie, Haoyang Luo, Yixuan Hu, Yaoyu Tao, Xiyuan Tang, Yuan Wang, Runsheng Wang, Meng Li. A 28nm 534.6 TOPS/W mixed-precision edge accelerator for embodied AI using stochastic computing. IEEE Asian Solid-State Circuits Conference (A-SSCC), 2025. Search
21 Minghui Yin, Jiukai Fang, Longhao Yan, Zelun Pan, Bowen Wang, Zhe Zhan, Xile Wang, Yaoyu Tao, Yuchao Yang. A hybrid analog-digital RRAM CIM system with 4T2R1C charge-domain ACIM and RL-driven mixed-precision deployment for AI inference. IEEE European Solid-State Electronics Research Conference (ESSERC), 2026. Program Search
22 Bowen Wang, Zelun Pan, Zhe Zhan, Longhao Yan, Jiukai Fang, Xile Wang, Yuqi Li, Minghui Yin, Xi Li, Zhitang Song, Yaoyu Tao, et al. A 40nm 3.58 mJ/frame PCM-based POSIT/INT mixed-precision digital/analog CIM chip for edge foveated rendering. IEEE European Solid-State Electronics Research Conference (ESSERC), 2026. Program Search
23 Yanghao Wang, Pek Jun Tiw, Yaoyu Tao, Teng Zhang, Yuchao Yang. Harnessing Turing instability through VO2-based negative feedback loop coupling system. IEEE European Solid-State Electronics Research Conference (ESSERC), 2025. Search
24 Bowen Wang, Longhao Yan, Xiyuan Tang, Xile Wang, Yuqi Li, Zeyu Wang, Zelun Pan, Daijing Shi, Zhe Zhan, Yaoyu Tao, Zhitang Song, Yuchao Yang. A 617.7 TOPS/W PCM-based charge-domain CIM macro with capacitor reuse method and scalable local compute unit. IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 2025. IEEE Xplore Search
25 Xile Wang, Longhao Yan, Xi Li, Yaoyu Tao, Zhitang Song, Yuchao Yang. An efficient pipeline programming scheme based on 40nm PCM compute-in-memory chip for CNNs. IEEE Electron Devices Technology and Manufacturing (EDTM), 2025. Search
26 Quan Zhang, Longhao Yan, Yaoyu Tao, Ru Huang, Yuchao Yang. On-chip write and verify and endurance enhancer circuits towards multi-level RRAM array. IEEE Electron Devices Technology and Manufacturing (EDTM), 2024: 1–3. Search
27 Wenshuo Yue, Zhaokun Jing, Bonan Yan, Yaoyu Tao, Teng Zhang, Ru Huang, Yuchao Yang. Multifunctional RRAM chip with configurability for sparsity-aware in-memory Ising machine. IEEE Conference of Science and Technology for Integrated Circuits (CSTIC), 2024. Search
28 Chia-Hsiang Chen, Yaoyu Tao, Zhengya Zhang. Efficient in situ error detection enabling diverse path coverage. IEEE International Symposium on Circuits and Systems (ISCAS), 2013: 773–776. Best paper nomination Search

Academic impact

The work has been cited and assessed by scholars in the field, and the circuit designs have been cited in commercial patents by technology companies.

ScholarCitation and assessment
Muriel Médard(NAE member, MIT)Cited and assessed as representative work in beyond-Moore chip architecture and ICs for intelligent algorithms
Erdal Arıkan(inventor of polar codes, Shannon Award, IEEE Fellow)Cited as representative work in beyond-Moore chip architecture and ICs for intelligent algorithms
Naresh Shanbhag(SIA University Researcher Award, Jack Kilby Professor, UIUC, IEEE Fellow)Assessed as representative work in beyond-Moore chip architecture and ICs for intelligent algorithms
Xiaohu You(Member, Chinese Academy of Sciences)Cited as a representative result in beyond-Moore chip architecture and ICs for intelligent algorithms
Francis Chi Moon Lau(Professor, HKU, IEEE Millennium Medal)Cited as representative work in beyond-Moore chip architecture and ICs for intelligent algorithms
Hideki Ochiai(Professor, Osaka University, IEEE Fellow)Cited as representative work in beyond-Moore chip architecture and ICs for intelligent algorithms
Yeong-Luh Ueng(Wu Ta-You Memorial Award, Professor, NTHU)Noted the substantial reduction in data communication energy
Andreas Peter Burg(Professor, EPFL, Editor-in-Chief, IEEE TVLSI/TSP)Cited as representative work on successive-cancellation list decoder chips
Warren Gross(Chair, ECE, McGill University)Cited as a representative chip in signal processing

The circuit designs have additionally been cited in commercial patents by Huawei, Qualcomm and SK hynix.