学术合作
Collaboration
Cross-layer research is hard to do alone. Device processing, materials characterisation and system deployment each have a steep barrier of their own, and most of the lab's work rests on a long-standing division of labour with partners.
Within Peking University
The lab is based jointly in the School of Integrated Circuits and the Institute for Artificial Intelligence, with long-running joint projects across several groups.
- Prof. Yixin Zhu's group (Institute for AI) Neural dynamics modelling, 3D manifold reconstruction and embodied intelligence tasks, providing application-side validation for the chips.
- Prof. Yaodong Yang's group (Institute for AI) Reinforcement learning and multi-agent decision making, supporting algorithm mapping and scheduling strategies for compute-in-memory chips.
- Prof. Bonan Yan's group (School of Integrated Circuits) Probabilistic computing accelerators, CIM instruction sets and causal inference hardware.
- Prof. Meng Li's group (School of Integrated Circuits) Mixed-precision quantization, stochastic computing and edge accelerators.
- Prof. Xiyuan Tang (School of Integrated Circuits) Low-power analogue front ends and CIM peripheral circuits.
- Prof. Qian Wang's group (School of Psychological and Cognitive Sciences; IDG/McGovern Institute for Brain Research) Invasive brain–computer interfaces and cognitive neuroscience, guiding the application requirements for BCI and brain-state modelling.
- Yuanpei College and the School of EECS Joint undergraduate curriculum development and research training.
Research institutes
- Shanghai Institute of Microsystem and Information Technology, CAS (Prof. Zhitang Song's group) Provides the phase-change memory process platform and devices; joint work includes the 40nm mixed-precision phase-change CIM chip, the 64-core phase-change CIM processor and the neural dynamical system chip.
- Beijing Academy of Artificial Intelligence Supports the work through the Qingyuan Scholar programme and provides a cross-disciplinary forum.
- PKU Wuhan Institute for Artificial Intelligence Joint work on a vision compute-in-memory chip fusing memristors and SRAM.
- Shanghai Institute of Technical Physics, CAS Support in infrared optoelectronic devices and sensing-storage-compute intelligent perception.
- School of Integrated Circuits, Tsinghua University Exchange and collaboration on compute-in-memory architecture and emerging devices.
- National Engineering Research Center for Si-based LEDs (Nanchang University) Collaboration on silicon-based GaN optoelectronic devices, providing the light-source and photodetector basis for optoelectronic chip architecture. The centre's work on V-shaped-defect 3D PN junctions received a first prize in the 2025 National Natural Science Awards.
Industry
Industrial work centres on joint technical development and circuit IP delivery, with research questions drawn from real workloads and process constraints.
| Partner | Form | Focus and progress |
|---|---|---|
| Huawei | Young Talent Program; computing and data communication product line collaborations | Next-generation chip architecture; end-to-end compute-in-memory deployment (16.6× speedup); low-power FEC. Recipient of the 2024 Huawei Computing Product Line Best Technical Collaboration Award and the 2025 Huawei Weiming Young Scholar Award |
| Alibaba DAMO Academy | Circuit IP trial | AI computing circuit IP in trial deployment |
| Vertilite | Technical collaboration | VCSEL sensing-storage-compute chip and hardware system (2024.06–2026.06) |
| Moore Nanotech (Hangzhou) | Technical collaboration | Micro/nano optical devices and waveguide processing, supporting photonic device fabrication and packaging for optoelectronic chip architecture |
| Xinyao Yuedong (Beijing) Technology Co., Ltd. | Application collaboration | Optical computing chips and circuits |
| SMIC, CASIC and others | Application collaborations | Process platforms and application scenarios |
Related patented technology has reached volume production in chips at Huawei and other companies.
International
The work has been cited and assessed by international peers, and the lab maintains academic exchange with several universities.
University of Michigan
Continued joint publication on beyond-Moore chip architecture and integrated circuits for intelligent algorithms, including heterogeneous system-in-package and neural ODE acceleration.
Stanford University
A basis for collaboration in high-fidelity sensor interfaces.
European and Japanese peers
Citation and exchange with researchers at EPFL, McGill and Osaka University on beyond-Moore chip architecture and ICs for intelligent algorithms.
Peer assessment
| Scholar | Citation and assessment |
|---|---|
| Muriel Médard, NAE member, Professor at MIT | Cited and assessed as representative work in beyond-Moore chip architecture and ICs for intelligent algorithms |
| Erdal Arıkan, inventor of polar codes, Shannon Award laureate, IEEE Fellow (Bilkent University) | Cited as representative work in the field |
| Naresh Shanbhag, SIA University Researcher Award, Jack Kilby Professor at UIUC, IEEE Fellow | Assessed as representative work in the field |
| Xiaohu You, Member of the Chinese Academy of Sciences (Southeast University) | Cited as a representative result in the field |
| Francis Chi Moon Lau, Professor at HKU, IEEE Millennium Medal | Cited as representative work in the field |
| Hideki Ochiai, Professor at Osaka University, IEEE Fellow | Cited as representative work in the field |
| Yeong-Luh Ueng, Wu Ta-You Memorial Award, Professor at NTHU | Noted the substantial reduction in data communication energy; cited as representative work in the field |
| Andreas Peter Burg, Professor at EPFL, Editor-in-Chief of IEEE TVLSI/TSP | Cited as representative work on successive-cancellation list decoder chips |
| Warren Gross, Chair of ECE at McGill University | Cited as a representative chip in signal processing |
Academic service
Program committees
Technical program committee member for MICRO, HPCA and ISCAS; member of the IEEE ISCAS technical committee (2019, 2020).
Editorial boards
Nature npj Unconventional Computing (2024–); IEEE Transactions on Circuits and Systems I (2019); IEEE Young Professionals in CAS (2019).
Reviewing
Reviewer for Nature, Nature Electronics, Nature Communications, IEEE JSSC, IEDM, VLSI, FPGA, MICRO, HPCA and TCAS-I.
Ways to work together
The lab is open to the following kinds of collaboration and welcomes enquiries from universities, institutes and companies.
- Joint technical development A project defined around a specific compute bottleneck or efficiency target, with both sides contributing people and sharing results as agreed.
- Circuit IP licensing and customisation Existing in-memory operator circuits and coding circuits can be licensed or re-implemented for a particular process.
- Joint chip prototyping Shared multi-project wafer runs, with the lab contributing architecture and circuit design and the partner providing process and test support.
- Shared tooling Device models, architecture simulators and validation frameworks can be connected to a partner's software stack.
- Visiting scholars and joint supervision Short-term visiting researchers are welcome, and graduate students can be co-supervised with partner institutions.